1. Field of the Invention
The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a self-aligned process flow for forming vias.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of circuit functions. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines and the spaces between the metal lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit area.
In such modern integrated circuits, a limiting factor of device performance is the signal propagation delay caused by the switching speed of the transistor elements. As the channel length of these transistor elements has now reached 50 nm and less, the signal propagation delay is no longer limited by the field effect transistors. Rather, the signal propagation delay is limited, owing to the increased circuit density, by the interconnect lines, since the line-to-line capacitance (C) is increased and also the resistance (R) of the lines is increased due to their reduced cross-sectional area. The parasitic RC time constants and the capacitive coupling between neighboring metal lines, therefore, require the introduction of a new type of material for forming the metallization layers.
Traditionally, metallization layers, i.e., the wiring layers including metal lines and vias for providing the electrical connection of the circuit elements according to a specified circuit layout, are formed by embedding copper lines and vias in a dielectric layer stack. For highly sophisticated applications, in addition to using copper and/or copper alloys, the well-established and well-known dielectric materials silicon dioxide (k≈4.2) and silicon nitride (k>7) may increasingly be replaced by so-called low-k dielectric materials having a relative permittivity of approximately 3.0 and less.
In addition, the continuous reduction of the feature sizes with gate lengths of approximately 40 nm and less may demand for even more reduced dielectric constants of the corresponding dielectric materials. For this reason, it has been proposed to introduce “air gaps,” at least at critical device areas, since air or similar gases may have a dielectric constant of approximately 1.0.
Process flows for forming air gaps and multiple metallization layers are complex. The formation of the multiple metallization layers often requires the use of cap layers, such as silicon nitride, between the layers. Since the cap layer material has a dielectric constant higher than the low-k dielectric layer, the overall capacitance of the stack is increased, thereby reducing the maximum achievable switching speed.
The present disclosure is directed to various methods for forming vias and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.